1. Field of the Invention
The invention relates to relaxation oscillators for use in PLL circuits and in particular to current controlled oscillators without start-up or amplitude control problems used in PLLs for automatic time-constant or bandwidth tuning of gm-C filters.
2. Description of the Related Art
The design of a two-integrator based sinusoidal quadrature oscillator, which is widely used in phase locked loop (PLL) bandwidth tuning of gm-C filters (where gm-C stands for transconductance-Capacitor), is associated with amplitude control/start-up problems. See Khen Sang Tan and Paul R. Gray, xe2x80x9cFully Integrated Analog Filters Using Bipolar-JFET Technologyxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. SC-2, pp. 814-821, December 1978, and John M. Khoury, xe2x80x9cDesign of a 15 MHz CMOS Continuous-Time Filter with On-Chip Tuningxe2x80x9d, IEEE Journal of Solid-State Circuits vol. SC-26, no. 12, pp. 1988-1997, December 1991.
The above-mentioned PLL-based bandwidth-tuning scheme is shown in FIG. 1 and the two-integrator based quadrature sinusoidal current controlled oscillator (CCO) based on the traditional concept is shown in FIG. 2. The PLL-based bandwidth-tuning scheme 10 of FIG. 1 is comprised of phase detector (PD) 12, a charge pump (CP) 14, a loop filter (LF) 16, a voltage to current converter (VIC) 18, and a current controlled oscillator (CCO) 20. Block 12 receives as input the reference frequency fREF and from block 20 the feedback input f0. Block 12 feeds block 14 which feeds block 16. The output of block 16 is a voltage which get converted by block 18 to the current Itunc, Signal Itunc feeds other blocks for tuning (not shown) and block 20. FIG. 2 is a more detailed diagram of CCO 20 which shows transconductance amplifiers 22 and 24 coupled in series, each with a transconductance of gm. The output OUT 2 of 22 is coupled to the negative input IN4 of 24. The output OUT4 of 24 feeds the positive input IN2 of 22. The negative input of 22 and the positive input of 24 are grounded. Blocks 22 and 24 receive equal signals Itune 28 and 29, respectively. The outputs OUT2 and OUT4 are coupled via equal capacitors 26 and 27, respectively, to ground. This type of sinusoidal oscillators suffers from amplitude control and startup problems
U.S. Patents which have some bearing on the present invention are:
U.S. Pat. No. 6,201,450 (Shakiba et al) describes a relaxation oscillator which provides a very wide linear range of frequency variation versus control voltage (or current). U.S. Pat. No. 6,111,467 (Luo) discloses a time constant tuning circuit which uses a frequency of a clock to tune the circuit time constant. U.S. Pat. No. 6,084,465 (Dasgupta) describes a time constant tuning circuit in which a reference clock frequency is used to adjust the gm of a transconductor. U.S. Pat. No. 6,060,957 (Kodmja et al.) teaches a relaxation oscillator with low phase noise particularly applicable to PLLs. U.S. Pat. No. 6,020,792 (Nolan et al.) describes a precision relaxation oscillator with temperature compensation to produce a stable clock frequency. U.S. Pat. No. 5,497,127 presents a voltage controlled oscillator with a wide range of frequencies and which includes a relaxation oscillator. U.S. Pat. No. 5,489,878 (Gilbert) discloses an oscillator which includes two gm/C stages. U.S. Pat. No. 5,418,502 (Ma et al.) teaches the use of an R-C relaxation oscillator where two comparators control the charge/discharge of the capacitor via an SCR. U.S. Pat. No. 5,093,634 (Khoury) shows using a triple input, triple output linear transconductance amplifier as an oscillator by feeding back the output of the amplifier to the input. U.S. Pat. No. 5,070,311 (Nicolai) describes using current sources, selected by a register, to control the charge/discharge of a capacitor and thereby adjusting the frequency of an oscillator. U.S. Pat. No. 4,977,381 (Main) presents a relaxation oscillator where the direction of the current to the capacitor in the oscillator is alternated, based on the state of a bistable circuit. U.S. Pat. No. 4,963,840 (Thommen) is similar to U.S. Pat. No. 4,977,381 above but in addition reduces power consumption. U.S. Pat. No. 4,725,993 (Owen et al.) discloses a low duty cycle relaxation oscillator which periodically gates an ultrasonic frequency relaxation oscillator. U.S. Pat. No. 4,377,790 (Zobel et al.) teaches a relaxation oscillator where a capacitor is charged and discharged between an upper and lower voltage level based on a signal from a comparator. U.S. Pat. No. 4,535,305 (Matsuo et al.) describes a transmission gate relaxation oscillator using a comparator which compares the charge/discharge voltage with a reference voltage. The invention is different from all of the above cited U.S. Patents.
The invention below describes several equivalent relaxation CCOs that overcome startup/amplitude control problems of sinusoidal CCOs, are simple to design and totally compatible with modern PLL circuits.
It is an object of at least one embodiment of the present invention to provide a circuit and a method for a relaxation current controlled oscillator (CCO) for phase locked loop (PLL)-based time constant tuning of gm-C filters.
It is another object of the present invention to provide a CCO which does not have amplitude control problems.
It is yet another object of the present invention to provide a CCO which does not have start-up problems.
It is still another object of the present invention to provide a CCO which is simple to design and is totally compatible with modem PLL circuits.
It is a further object of the present invention is to provide a CCO where there is great flexibility in choosing the reference frequency fREF or the oscillation frequency f0.
It is yet a further object of the present invention is to provide a CCO with a truly 50% duty cycle output waveform.
It is still a further object of the present invention is to provide a CCO with a non overlapping output waveform.
These and many other objects have been achieved by forming a test integrator out of a transconductance amplifier and a capacitor. The output of the integrator is fed to comparators which in turn feed a bistable circuit such as a SR flip flop. The output Q and its inverse QB of the bistable circuit controls either the polarity of the input signals to the transconductance amplifier or the polarity of the input signals to the comparators (when the transconductance amplifier has a differential output). Switches, controlled by the bistable circuit, in turn control the polarity of the input signals. The feedback path created by the transconductance amplifier, comparators, flip-flops, and switches causes continuous oscillation to take place. A DC current input adjusts the gm of the transconductance amplifier allowing the oscillation frequency of the CCO to be adjusted by varying the DC current input. There is great flexibility in choosing the reference frequency fREF or the oscillation frequency f0 by the proper choice of a resistive divider.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.